CS gate 2003 Question About Paging...

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CS gate 2003 Question About Paging...

Postby aswinkgopan » Wed Nov 26, 2014 2:39 pm

A processor uses 2-level page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both 32 bits wide. The memory is byte addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are used as index into the first level page table while the next 10 bits are used as index into the second level page table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-aside buffer (TLB), with a hit rate of 96%. The TLB caches recently used virtual page numbers and the corresponding physical page numbers. The processor also has a physically addressed cache with a hit rate of 90%. Main memory access time is 10 ns, cache access time is 1 ns, and TLB access time is also 1 ns. Assuming that no page faults occur, the average time taken to access a virtual address is approximately (to the nearest 0.5 ns).

I have produced the answer to the above question. But its the second part that i am getting confused.

Total time = TLB HIT RATIO * { TLB ACCESS TIME + CACHE HIT RATIO ( CACHE ACCESS TIME ) +
CACHE MISS RATIO ( CACHE ACCESS TIME + MEMORY ACCESS TIME) }
+ TLB MISS RATIO * { TLB ACCESS TIME + PAGE 1 ACCESS TIME + PAGE 1 ACCESS TIME
* CACHE HIT TIME(CACHE ACCESS TIME) +
CACHE MISS RATIO(MEMORY ACCESS TIME + CACHE ACCESS TIME)}

For the above I am getting 4ns as the answer.

Q2) Suppose a process has only the following pages in its virtual address space: two contiguous code pages starting at virtual address 0x00000000, two contiguous data pages starting at virtual address 0×00400000, and a stack page starting at virtual address 0×FFFFF000. The amount of memory required for storing the page tables of this process is:

The below is my understanding of the question. Please let me know how to go about it.

Date Page : 0x00000000 ( 2 pages)
[0000 0000 00] [00 0000 0000] [0000 0000 0000]
[1st page_addr] [2nd page_addr] [offset]

Code Page : 0x000400000 ( 2 pages)
[0000 0000 01] [ 00 0000 0000 ] [0000 0000 0000]
[1st page_addr] [2nd page_addr] [offset]

Stack Page :0xFFFFF000 (1 pages)
[1111 1111 11] [11 1111 1111] [0000 0000 0000]
[1st page_addr] [2nd page_addr] [offset]

So the 2 data virtual page address for data page :
[0000 0000 00] [00 0000 0000] [0000 0000 0000]
[0000 0000 00] [00 0000 0001] [0000 0000 0000]

and similarly 2 virtual page address for code page :
So the two data page virtual address would be :
[0000 0000 01] [00 0000 0000] [0000 0000 0000]
[0000 0000 01] [00 0000 0001] [0000 0000 0000]

and similarly 1 Stack page the virtual page address :
[1111 1111 11] [11 1111 1111] [0000 0000 0000]

Date Page : 1 entry for Data page table 1 (4 byte) and corresponding all entries of 2nd page table (1024 bytes) = 4kb
Code Page : 1 entry for Code page table 1 (4 byte) and corresponding all entries of 2nd page table (1024 bytes) = 4kb
Stack Page : 1 entry for Stack page table 1 (4 byte) and corresponding allentries of 2nd page table (1024 bytes) = 4kb

So total memory should be 12kb...right ? But actual answer given is 16kb..
Please let me know what i am missing here..

Thanking you guys in advance...
aswinkgopan
 
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